1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly to a dynamic random access memory (DRAM) device. More specifically, the present invention is concerned with a read operation of such a DRAM device in which data is read from a memory cell of the DRAM device.
2. Description of the Related Art
FIG. 1 is a circuit diagram of a part of a conventional DRAM device. The circuit configuration shown in FIG. 1 relates to a pair of bit lines BL and /BL. The DRAM device shown in FIG. 1 includes a sense amplifier part 10 and two cell array parts 12 and 14 connected to the sense amplifier part 10. The sense amplifier part 10 is commonly connected to the two cell array parts 12 and 14. The cell array part 14 has the same circuit configuration as that of the cell array part 12, and thus the internal configuration of the cell array part 14 is omitted in FIG. 1 for the sake of simplicity.
The cell array part 12 includes a plurality of memory cells MC connected to the pair of bit lines BL and /BL. The cells MC are alternately connected to the bit lines BL and /BL in a folded-type bit line formation. Each of the memory cells MC consists of one capacitor and one transistor. The cell array part 12 also includes a transistor which receives a bit line reset signal BRST, which instructs the transistor to short-circuit the bit lines BL and /BL and precharge these bit lines to a voltage of VCC/2, where VCC is a high-potential-side power supply voltage.
The sense amplifier part 10 includes a flip-flop circuit 16, a data input/output circuit 18 and transfer gate circuits 20 and 22. The flip-flop circuit 16, which is made up of four transistors, sets the potential of one of the bit lines BL and /BL to one of control signals PSA and NSA and sets the potential of the other bit line to the other control signal. Each of the transfer gate circuits 20 and 22 includes two transistors respectively connected to the bit lines BL and /BL. The transfer gate circuits 20 and 22 operate in response to transfer control signals BT0 and BT1 so that one of the cell array parts 12 and 14 is connected to the sense amplifier part 10. The data input/output circuit 18 includes two transistors, and connects the bit lines BL and /BL to data bus lines DB and /DB (two bus lines of a data bus) in response to a column select signal CL.
FIG. 2 is a waveform diagram of a read operation of the DRAM device shown in FIG. 1. It will now be assumed that the DRAM device operates in synchronism with a clock signal CLK having one cycle of 10 ns. One cycle of the read operation is carried out in accordance with a row address command ROW, a column address command COL, and a bit line precharge command PRE, and is equal to 90 ns.
The row address command ROW is externally applied to the DRAM device in a state in which the bit lines BL and /BL are at the precharge (reset) level equal to VCC/2. The row address is decoded by a row address decoder, which is not shown in FIG. 1. Then, the decoder drives a corresponding word line. It will now be assumed that a word line WL shown in FIG. 1 is driven. The word line WL rises toward the high-potential-side power supply voltage VCC from a low-potential-side power supply voltage VSS. The potential of one of the bit lines which is located on the selected side is changed in accordance with data (binary data "0" or "1") stored in the cell MC connected to the selected word line WL. In FIG. 2, the bit line BL is located on the selected side (that is, the cell MC connected to the selected word line WL is connected to the bit line BL). Further, the selected cell MC stores data "0". In this case, the potential of the bit line BL starts to decrease from VCC/2. At this time, the potential of the not-selected-side bit line /BL is maintained at VCC/2.
The sense amplifier part 10 senses the relative potential change between the bit lines BL and /BL. Hence, as shown in FIG. 2, the potential of the bit line BL is drawn to VSS and the potential of the bit line /BL is drawn to VCC.
After the sense amplifier part 10 starts the sense operation, the column select signal CL is turned ON (activated) in response to the column address command COL. Then, the potentials of the bit lines BL and /BL settled by the sense amplifier part 10 are respectively output to the data bus lines DB and /DB via the data input/output circuit 18. This output operation is indicated as "DATA" in FIG. 2. Simultaneously, the bit line precharge command PRE is externally received, and the bit line reset signal BRST is activated. Hence, the bit lines BL and /BL are precharged (reset) to VCC/2. Hence, the DRAM device is ready for the next read operation. In the above-mentioned manner, the one cycle of the read operation is carried out.
However, the above prior art DRAM device has the following disadvantage.
As described above, the read operation needs the precharge operation in which the bit lines BL and /BL are precharged to VCC/2. More particularly, one cycle of the read operation includes the time necessary to precharge the bit lines BL and /BL to VCC/2. This prevents speeding up of the read operation.